The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory device using a cyclic redundancy code (CRC) checking, and a method for driving the same.
A system is implemented with a plurality of semiconductor devices. Among them, a semiconductor memory device is used to store data. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores the data received from the data processor into unit cells corresponding to addresses input together with the data.
As the operating speed of the system is increasing, the data processor requires the semiconductor memory device to input/output data at a higher speed. As semiconductor integrated circuit (IC) technologies are rapidly developed, the operating speed of the data processor increases, but the data input/output speed of the semiconductor memory device does not keep up with the increased operating speed of the data processor.
Many attempts have been made to develop semiconductor memory devices that can increase data input/output speed up to the level required by the data processor. One of these semiconductor memory devices is a synchronous memory device that outputs data at each period of a system clock. Specifically, the synchronous memory device outputs or receives data to or from the data processor in synchronization with the system clock. However, because even the synchronous memory device could not keep up with the operating speed of the data processor, a double data rate (DDR) synchronous memory device was developed. The DDR synchronous memory device outputs or receives data at each transition of the system clock. That is, the DDR synchronous memory device outputs or receives data in synchronization with falling edges and rising edges of the system clock.
Meanwhile, in order to meet the required data processing speed of the data processor, the number of bits of inputted/outputted data in response to one-time data access command, i.e., a read command or a write command, is gradually increasing. That is, the number of inputted/outputted data in parallel during one-time data access operation is gradually increasing. For example, while 4-bit data have been inputted/outputted in response to the one-time data access command, the number of data is increased such that 8-bit or 16-bit data are inputted/outputted. In other words, the number of data processed by the one-time data access command is increased so as to meet the required data transfer speed of the system.
However, since the increase in the number of data processed by the one-time data access command causes a serious problem, it is very difficult to increase the number of data to more than a predetermined number. When the number of data inputted/outputted in response to the one-time data access command increases, the number of data input/output pads in the semiconductor memory device must increase. In addition, the number of data lines in the semiconductor memory device must increase as many as the increased number of the data input/output pads. Further, data lines between the semiconductor memory device and the data processor must also increase. The respective data lines are mutually influenced seriously when a plurality of data lines are arranged in parallel in such a state that data are transferred through the respective data lines at high speed. In some serious cases, data signals loaded on adjacent data lines are inverted and thus data are incorrectly changed.
As the operating speed of the semiconductor processor is further increased with the rapid advance of the semiconductor integrated circuit technology, even the data input/output speed of the DDR synchronous memory device may not meet the data input/output speed required by the semiconductor memory device. As described above, the required bandwidth of the system can be met by increasing the number of inputted/outputted data in parallel. However, since this method has already reached its limitation, a new semiconductor memory device and a method for driving the same are required.
As one approach to significantly increasing the operating speed of semiconductor memory devices, a variety of data transfer methods used in communication systems are applied to semiconductor memory devices. A typical method is to input/output data in series, not in parallel. As one example, after transferring data between the semiconductor memory device and the data processor, data error is checked using an error check code. The most typical method is a cyclic redundancy code (CRC) checking method. According to the CRC checking method, a check bit is generated using a predetermined number of data and then is output when the predetermined number of data are output. A device receiving the predetermined number of data compares the check bit with data so as to determine if the data is inputted normally. The CRC checking method makes it possible to input/output data at high speed. Therefore, when the data access command is inputted, it is unnecessary to increase the number of data processed in parallel so as to meet the required data transfer speed of the system.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device 10D using a CRC checking method includes a cell array 110, a CRC check circuit 120, a CRC generation circuit 130, a write signal transfer circuit 140, and a read signal transfer circuit 150. During a write operation, the semiconductor memory device 100 receives a write command, a write data, and a write address through a write signal input port LWI. The CRC check circuit 120 uses a CRC to check if an error occurs in the inputted write data. When no error is found, the CRC check circuit 120 stores the write data according to a corresponding address. When the error is found, the CRC check circuit 120 requests a retransmission of the write data through a write signal output port LWO and again receives the write data. During a read operation, the semiconductor memory device 100 receives a read command and a read address through a read signal input port LRI. The semiconductor memory device 100 outputs data of the cell array corresponding to the read address through a read signal output port LRO. The CRC check circuit 130 generates a CRC code corresponding to the outputted data and outputs the CRC code when data are outputted in response to the read command. A data processor receiving the data from the semiconductor memory device compares the inputted CRC with the received data to check if an error exists in the received data. When the error exists, the CRC check circuit 120 requests the semiconductor memory device to output the data again. When no error exists, the semiconductor memory device performs an operation using the received data.
Using the CRC, the data can be inputted/outputted at high speed without increasing the number of data transfer paths in parallel between the semiconductor memory device and the data processor.
However, the operation of generating the CRC in the data transfer is added. Therefore, there is a need for a method for efficiently generating the CRC.